In prior-art wafers, poly silicon plugs (contact plugs) are often used as vertical interconnects between metal lines in multilevel interconnect schemes. The ferroelectric materials in FeRAM (Ferroelectric Random Access Memory) and high K materials in DRAM generally are crystallized at a high temperature (600C or above) in oxygen ambient. A thick barrier against oxygen diffusion is needed to prevent the diffusion of oxygen from a ferroelectric capacitor to the contact plug. An Ir (Iridium) based barrier is a good material to efficiently block this oxygen diffusion. A typical hardmask used during the etching of this Ir barrier is made from TEOS (Tetraethyl Orthosilicate). Due to the low etching selectivity between Ir and TEOS, the thickness of the barrier is limited by the maximum usable hardmask thickness and the TEOS hardmask needs to be very thick compared to the capacitor stack, resulting in a steep side wall angle prior to etching.
FIGS. 1-3 show conventional hardmask etching steps for ferroelectric capacitors.
FIG. 1 shows a wafer 1 following prior art processing steps. Following deposition of a ferroelectric stack, a top electrode (TE) 6 is covered with a TEOS hardmask 2 and mask resist strip patterning of the top electrode 6 is performed using halogen or CO-based chemistry to etch materials such as Iridium, Platinum, Iridium Oxide or various conductive oxide films. A portion of an underlying ferroelectric layer 8 (for example, PZT, SBT, or BLT) might also be etched during this step. A ferroelectric (FE) capacitor 5 is formed from portions including the top electrode 6, ferroelectric layer 8 and a bottom electrode (BE) 3 as shown in the magnified view in the figure.
A Ti glue-layer 7 serves to adhere the bottom electrode 3 to the substructure of the FE capacitor 5. The substructure includes a top TEOS layer 15 covering a top nitride layer 9. Between the Ti glue-layer 7 and the bottom electrode 3 can be layers 17 of Ir (Iridium), IrO2 (Iridium Oxide) or other materials for blocking oxygen diffusion. A poly silicon contact plug 13 passes through the wafer 1 to form an electrical connection between an active region and the bottom electrode 3.
Another TEOS hardmask 4 is deposited in preparation for a second etching step which patterns the bottom electrode 3. During the second etching step, the ferroelectric layer 8 may be further etched along with the bottom electrode 3. There is a slight over-etch through the top TEOS layer 15 along with any intermediate materials such as the layers of Ir (Iridium) and IrO2 (Iridium Oxide). FIG. 2 shows the wafer 1 following this conventional patterning of the bottom electrode 3.
FIG. 3(a) shows the thick hardmask 4 having steeply angled sidewalls 19 which is required due to the low selectivity between the ir of the barrier layer 17 and the TEOS of the hardmask 4. It is desirable to have a thick Ir layer for blocking oxygen diffusion from the ferroelectric layer 8 to the poly silicon contact plug 13, but this is not easily done because it requires a very thick hardmask 4 with the resulting steeply angled sidewalls 19.
FIG. 3(b) shows the wafer of FIG. 3(a) after sputtered controlled etching of the bottom electrode 3 and barrier 17 while using the hardmask 4 for patterning the bottom electrode 3. Due to the steeply angled hardmask sidewalls 19, residues of the etching process or fences 21 remain clinging to the hardmask sidewalls 19. These fences 21 are composed of compounds from the etched materials. They have low density and are unstable. During the anneals, they exhibit volume changes and they show poor adhesion to the side walls. These fences 21 are particularly detrimental to the following encapsulation processes.
One way to avoid these fences 21 would be to use etching gasses which form exclusively volatile compounds. But these are often ruled out due to conflicting requirements, like capacitor damage or undercut of underlying layers. Thus, the etching inevitably proceeds, at least partially, in the sputter controlled regime.
It would be desirable to have a hardmask having a high etching selectivity relative to the barrier layer. In particular, it would be desirable to have a hardmask having a high etching selectivity relative to an Ir-based barrier layer.